1. Field of the Invention
The present invention relates to a master structure and a layout constitution of a gate array (GA) and an embedded array (EA).
2. Related Background Art
In recent years, with the popularization of portable electronic apparatuses such as notebook type computers, it has often been intended to reduce a packaging area by integrating peripheral circuits of CPU into one chip. Such a multifunctional chip is generally constituted using a gate array or an embedded array.
FIG. 1 is a layout diagram of a conventional gate array. The conventional gate array has an internal cell area 1 on which various logic circuits are formed, a pad area 2 connected to external wirings, and an I/O cell area 3 formed between the internal cell area 1 and the pad area 2. Each input/output terminal in the internal cell area 1 is connected to the corresponding pad in the pad area 2 through the I/O cell area 3.
In the pad area 2, a plurality of pads are formed at predetermined intervals. Each pad is connected to a corresponding external pin of a package (not shown) via a carrier tape (not shown).
The above-described multifunctional chip communicates with many kinds of external signals, and hence, a number of pads for external connection have to be disposed in the chip. In the conventional gate array, however, the pad area 2 is formed only on the outside periphery of the chip as shown in FIG. 1, so that the number of the pads cannot sufficiently be increased. Therefore, even when an empty space is present in the internal cell area 1 or the I/O cell area 3, there is a problem that the circuit cannot be formed because of the shortage of the pad area 2.